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Analysis and Design of a Minimum-Loss Discontinuous PWM Scheme for a Single-Inverter Dual-Parallel IPMSM Drive System

초록/요약

This thesis presents the analysis and design of a minimum-loss discontinuous pulse width modulation （MLDPWM） scheme for a single-inverter dual-parallel （SIDP） interior permanent magnet synchronous motor （IPMSM） drive system. The single objective of this thesis is to minimize the inverter switching loss of the SIDP IPMSM drive across its full load-imbalance range. The speed synchronization between the two motors is not a contribution of this work; it is already secured by the active damping controller and is treated throughout as a fixed operating constraint that the modulation scheme must preserve. A single three-phase two-level voltage source inverter supplies two IPMSMs whose stator terminals are connected in parallel, with one motor regulated by a cascaded vector controller and the other stabilized by an active damping controller. Because the inverter current is the vector sum of the two stator currents, its phase relative to the inverter voltage shifts with the load imbalance between the two motors. This shift causes conventional voltage-phase discontinuous pulse width modulation （DPWM） and conventional current-phase DPWM to lose their switching-loss-minimization property in opposite operating regions. The proposed MLDPWM combines a current-phase clamping rule with a voltage phase based rail-clamping rule and selects between them according to the load imbalance ratio, with a hysteresis band to suppress chattering. The zero-sequence offset voltage is synthesized in carrier-based form so that the scheme is implementable on a standard digital signal processor without modifying the existing current loop. The inverter switching loss is modeled using a linear energy-per-event formulation referenced to representative IGBT datasheet parameters. The MLDPWM strategy reduces inverter loss by aligning the clamping interval with the phase carrying the largest instantaneous resultant current whenever current peak detection remains reliable. Since the energy dissipated during a switching event is proportional to the current at the switching instant, suppressing switching transitions in the highest current phase reduces the dominant switching loss component. The remaining switching transitions occur in phases carrying lower instantaneous currents, which further supports the minimum loss objective. The proposed method is verified through time-domain PSIM simulation under balanced, mild-imbalance, and severe-imbalance operating conditions and is compared against space vector pulse width modulation （SVPWM） and conventional DPWM. The simulation results indicate that the proposed scheme achieves the lowest total inverter loss across all tested operating conditions. The current quality and the primary-secondary speed synchronization are preserved within the design bounds.

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초록/요약

본 논문은 단일 인버터 듀얼 병렬（SIDP） 매입형 영구자석 동기 전동기（IPMSM） 구동 시스템을 위한 최소 손실 불연속 펄스폭 변조（MLDPWM） 기법의 해석 및 설계를 제안한다. 단일 3 상 2 레벨 전압형 인버터가 고정자 단자를 병렬로 연결한 두 대의 IPMSM 에 전력을 공급하며, 하나의 전동기는 종속 벡터 제어기에 의해 조절되고, 다른 전동기는 능동 제동 제어기에 의해 안정화된다. 인버터 전류는 두 고정자 전류의 벡터 합이므로, 두 전동기 간의 부하 불평형에 따라 인버터 전압에 대한 위상이 변화한다. 이로 인해 기존의 전압 위상 기반 불연속 펄스폭 변조（DPWM）와 전류 위상 기반 DPWM 은 서로 상반되는 운전 영역에서 스위칭 손실 최소화 특성을 상실한다. 제안하는 MLDPWM 은 전류 위상 클램핑 규칙과 전압 크기 기반 레일 클램핑 규칙을 결합하여, 부하 불평형 비율에 따라 두 방식 중 하나를 선택하며, 히스테리시스 대역을 통해 전환 경계에서의 채터링을 억제한다. 영 시퀀스 오프셋 전압은 반송파 기반 형태로 합성되어, 기존 전류 제어 루프를 수정하지 않고 표준 디지털 신호 처리기에 구현할 수 있다. 인버터 스위칭 손실은 대표적인 IGBT 데이터시트 파라미터를 기준으로 한 선형 에너지 공식으로 모델링된다. 제안 기법은 평형, 경미한 불평형, 심각한 불평형 운전 조건에서 PSIM 시간 영역 시뮬레이션을 통해 검증되었으며, 공간벡터 펄스폭 변조（SVPWM） 및 기존 DPWM 과 비교·평가되었다. 시뮬레이션 결과, 제안 기법은 모든 시험 운전 조건에서 가장 낮은 총 인버터 손실을 달성하였으며, 전류 품질과 주-부 전동기 간 속도 동기화는 설계 범위 내에서 유지됨을 확인하였다.

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목차

CHAPTER 1 INTRODUCTION 1
CHAPTER 2 SYSTEM MODELING OF THE SIDP IPMSM DRIVE 3
2.1 SIDP IPMSM DRIVE CONFIGURATION 3
2.2 TWO-LEVEL VOLTAGE SOURCE INVERTER MODEL 3
2.3 IPMSM MATHEMATICAL MODEL 5
2.4 REFERENCE FRAME RELATIONSHIP BETWEEN THE TWO MOTORS 7
2.5 RESULTANT INVERTER CURRENT AND LOAD IMBALANCE 7
2.6 PRIMARY-SECONDARY CONTROL STRUCTURE 8
CHAPTER 3 ANALYSIS OF CONVENTIONAL PWM STRATEGIES IN THE SIDP IPMSM DRIVE. 10
3.1 CONTINUOUS AND DISCONTINUOUS CARRIER-BASED PWM 10
3.2 VOLTAGE PHASE-BASED DPWM 11
3.3 RESULTANT CURRENT PHASE-BASED DPWM 12
3.4 VOLTAGE-CURRENT PHASE DEVIATION UNDER LOAD IMBALANCE 12
CHAPTER 4 PROPOSED MINIMUM-LOSS DPWM SCHEME 14
4.1 OPERATING REGIONS AND MODE SELECTION CRITERION 14
4.2 HYSTERESIS LOGIC FOR MODE TRANSITION 15
4.3 CARRIER-BASED OFFSET VOLTAGE SYNTHESIS 15
4.4 ALGORITHM IMPLEMENTATION 16
4.5 INVERTER LOSS MODEL 17
4.6 PERFORMANCE INDICES 18
CHAPTER 5 SIMULATION RESULTS 19
5.1 SIMULATION ENVIRONMENT AND PARAMETERS 19
5.2 BASELINE OPERATION VERIFICATION 21
5.3 RESULTANT CURRENT AND PHASE DEVIATION ANALYSIS 23
5.4 MODULATING SIGNALS AND MLDPWM MODE BEHAVIOR 24
5.5 INVERTER LOSS COMPARISON 26
5.6 CURRENT QUALITY AND SPEED SYNCHRONIZATION. 27
5.7 DISCUSSION 28
CHAPTER 6 CONCLUSION 29
REFERENCES 30
국문요약 32

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