Perovskite-structured High-k/Electrode Heterostructures to Reduce the Dead Layer Effect
Dead layer 효과를 줄이기 위한 페로브스카이트 유전막/전극막 이종 접합 구조에 대한 연구
- 주제(키워드) Perovskite materials , Atomic Layer Deposition , Dead layer effect , High-k , Electrode
- 주제(DDC) 621.042
- 발행기관 아주대학교 일반대학원
- 지도교수 이상운
- 발행년도 2026
- 학위수여년월 2026. 2
- 학위명 박사
- 학과 및 전공 일반대학원 에너지시스템학과
- 실제URI http://www.dcollection.net/handler/ajou/000000035474
- 본문언어 영어
- 저작권 아주대학교 논문은 저작권에 의해 보호받습니다.
초록/요약
t Dynamic random access memory (DRAM) functions as the main system memory and provides much faster access speeds than solid- state drives (SSDs) and hard disk drives (HDDs). Each DRAM cell is composed of a single transistor and a single capacitor. The transistor acts as a switching element that enables read and write operations by selecting the target cell through a word-line signal; it does not store information itself but simply connects the chosen cell to the bit line. The capacitor is the component that stores data: a stored electric charge represents a logic “1,” while the absence of charge corresponds to a logic “0.” Because DRAM is volatile, the stored charge gradually dissipates, requiring periodic refresh operations to preserve data, which makes sufficient capacitance critical for stable memory operation. In recent years, rapid progress in artificial intelligence has led to a dramatic increase in data processing demands. This has accelerated the adoption of high-bandwidth memory (HBM), where multiple DRAM layers are vertically integrated to support high-speed data transfer and computation. As a result, enhancing the data storage capability of DRAM has become increasingly important. As integration density continues to rise with ongoing device scaling, maintaining adequate cell capacitance has become increasingly difficult. Consequently, there is a growing need for atomic layer deposition (ALD) processes capable of forming dielectric materials with high dielectric constants. At present, DRAM capacitors employ a ZrO₂–Al₂O₃–ZrO₂ (ZAZ) stack based on ZrO₂, which has a dielectric constant of roughly 30. In future technology nodes, ternary HfZrOₓ (HZO) dielectrics with dielectric constants approaching 40 are expected to be introduced. Furthermore, the formation of a dead layer at the interface between high-k dielectrics and electrodes lowers the effective dielectric constant, thereby reducing overall capacitance. Addressing this issue requires the development of electrode materials that share the same perovskite crystal structure as the dielectric, along with compatible ALD processes. In this dissertation, a low-temperature alternative atomic layer deposition (ALD) route was developed for TiN thin films used as electrodes in DRAM capacitors, and the resulting reductions in impurity concentration and improvements in film resistivity were demonstrated. TiCl₄ and NH₃ were employed as the titanium and nitrogen precursors, respectively. In parallel, the development and characterization of perovskite-structured materials—considered promising candidates for next-generation DRAM capacitor dielectrics and electrodes—were investigated. A strategy to address interfacial oxidation between perovskite SrTiO₃ (STO) dielectric films and electrodes was proposed, and seed-layer-free in-situ crystallization of STO thin films was achieved. In addition, the ALD growth of a perovskite-structured SrVO₃ (SVO) electrode based on the transition metal vanadium was reported for the first time. Sr(iPrCp)₂, Ti(CpMe₅)(OMe)₃, and VO(acac)₂ were used as the strontium, titanium, and vanadium precursors, respectively, with H₂O, O₃, and O₂ serving as oxygen reactants. The deposition behavior of each ALD process was systematically analyzed, optimized through thin-film characterization, and the electrical performance was evaluated using fabricated metal–insulator–metal (MIM) capacitor structures.In this dissertation, a low-temperature alternative atomic layer deposition (ALD) route was developed for TiN thin films used as electrodes in DRAM capacitors, and the resulting reductions in impurity concentration and improvements in film resistivity were demonstrated. TiCl₄ and NH₃ were employed as the titanium and nitrogen precursors, respectively. In parallel, the development and characterization of perovskite-structured materials—considered promising candidates for next-generation DRAM capacitor dielectrics and electrodes—were investigated. A strategy to address interfacial oxidation between perovskite SrTiO₃ (STO) dielectric films and electrodes was proposed, and seed-layer-free in-situ crystallization of STO thin films was achieved. In addition, the ALD growth of a perovskite-structured SrVO₃ (SVO) electrode based on the transition metal vanadium was reported for the first time. Sr(iPrCp)₂, Ti(CpMe₅)(OMe)₃, and VO(acac)₂ were used as the strontium, titanium, and vanadium precursors, respectively, with H₂O, O₃, and O₂ serving as oxygen reactants. The deposition behavior of each ALD process was systematically analyzed, optimized through thin-film characterization, and the electrical performance was evaluated using fabricated metal– insulator–metal (MIM) capacitor structures. First, a low-temperature alternative ALD process was investigated for TiN, which is currently used as an electrode material in DRAM capacitors in the semiconductor industry. At a relatively low temperature of 400 °C, an ALD sequence of TiCl₄+HBr+NH₃ was developed by introducing HBr gas as an intermediate reactant. Based on Gibbs free energy calculations, it was confirmed that the introduction of HBr leads to the formation of TiBr₃ as an intermediate species, followed by a spontaneous substitution reaction resulting in TiN formation. Although HBr is generally known as an etching gas, it was confirmed that there was no difference in the ALD growth rate compared to the conventional TiN process. In the conventional TiN process, approximately 3% chlorine impurities remained in the film; however, in the process employing HBr gas, the chlorine impurity level was reduced to nearly 0%, and no bromine impurities were detected. To compare the crystallinity with that of conventional TiN, X-ray diffraction (XRD) analysis was performed, confirming identical crystallographic orientations corresponding to the (111), (200), and (220) planes. In addition, the ratio of processes using TiN and TiN– HBr was varied to investigate the correlation between impurity concentration and resistivity. As a result, incorporating HBr reduced the TiN resistivity by about 20% compared with the conventional TiN process, while lowering the impurity concentration from roughly 3% to nearly zero, thereby enabling the fabrication of a highly pure TiN thin film. Second, an in-situ ALD process for STO thin films was developed, and oxidation issues that may occur when depositing STO on perovskite electrodes were investigated. Conventionally, crystallization of STO thin films has been achieved using seed layers or post-deposition annealing; however, in this study, high crystallinity was obtained by depositing STO at relatively high process temperature of 350 °C led to STO’s in-situ crystallization without any additional treatment. SVO was used as the electrode material, and it was observed that oxidation of the SVO interface occurred due to the ozone as the oxygen source during STO deposition, forming an interfacial oxide layer. Since a TiO₂ thin film can block the penetration of ozone and thereby prevent interfacial oxidation, a model was proposed in which a passivation TiO₂ layer was first formed with H₂O as the primary oxygen source, followed by forming a TiO₂ layer with O₃ as the secondary oxygen source instead of the conventional TiO₂ process. Consequently, the density of the TiO₂ layer increased, and STO thin films were successfully deposited without interfacial oxidation. Furthermore, in- situ crystallized STO thin films exhibiting epitaxial growth along the lattice of the SVO electrode were demonstrated. This model was confirmed to be successfully applicable not only to SVO electrodes but also to TiN thin films. Third, a process development study was conducted for the atomic layer deposition of a perovskite-structured SrVO₃ (SVO) electrode to minimize the dead layer present at the interface between STO and the electrode and to enhance the electrical performaces of STO. As a preliminary study, an ALD process for VO₂ was developed, and the density and phase transformation of VO₂ were reported using a co- reactant. The VO₂ process development was subsequently applied to SVO, and the ALD process for SVO was reported for the first time. Partial crystallization at the interface was observed. Metal–insulator– metal (MIM) capacitors with an Au/Ti/STO/SVO structure were fabricated to evaluate the electrical characteristics. As a result, when the perovskite electrode SVO was employed, the dielectric constant (k) of STO, including interfacial effects, was reported to be 98, and the equivalent oxide thickness (Tₒₓ) was reported to be 4.3 Å. For an STO film with a thickness of about 10 nm, the leakage current density was measured to be 3 × 10⁻⁸ A/cm² at −0.8 V, corresponding to the DRAM operating voltage, and 8 × 10⁻⁸ A/cm² at +0.8 V. The dielectric loss was found to lie in the range of 0.006–0.01. In conclusion, this study aimed to improve the dielectric constant of DRAM capacitors by enhancing the interface between the dielectric and electrode thin films through process development via atomic layer deposition. A low-temperature alternative process was developed for TiN electrodes, allowing the fabrication of TiN thin films with impurity levels approaching zero. In addition, the process development of perovskite-based next-generation DRAM capacitor dielectrics and electrode thin films was carried out, and interfacial oxidation issues were successfully overcome by proposing a passivation model, which was also confirmed to be applicable to TiN electrodes. Furthermore, perovskite-structured SVO thin films were successfully implemented by ALD for the first time, and fabricated metal–insulator–metal (MIM) capacitors with STO dielectrics, the dead-layer effect was reduced. As a result, a dielectric constant of 98 for STO, including interfacial effects, approaching a value of 100, was achieved.
more초록/요약
Perovskite-structured high-k/electrode heterostructures to reduce the dead layer effect DRAM은 메모리 계층 구조에서 주기억장치로서 핵심적인 역할을 하며, AI 기술 발전에 따른 데이터 처리량 증가로 인해 메모리 대역폭과 커패시터 성 능의 중요성이 크게 부각되고 있다. DRAM의 미세화가 진행되면서 구조적 개선만으로는 셀 커패시턴스 유지에 한계가 도달하였고, 이에 따라 high-k 유전물질의 적용이 필수적이다. 그러나 high-k 유전막과 전극막 계면에서는 저유전율 층인 dead layer effect가 발생하여 전체 커패시턴스를 저하시키는 문제가 있다. 특히 유전막 두께가 10 nm 이하인 DRAM 커패시터에서는 이 문제가 치명적이며, 이를 해결하기 위한 계면 제어 기술이 요구된다. 본 연구는 원자층 증착법(ALD)을 기반으로 페로브스카이트 구조의 high-k 유전막과 전극막 이종접합에서 발생하는 계면 산화와 dead layer effect를 완 화하는 것을 목표로 하였다. 유전막으로는 높은 유전상수를 가지는 SrTiO₃(STO)를 적용하였고, 전극막으로는 현재 DRAM 커패시터 전극인 TiN 과 페로브스카이트 구조의 non-noble 금속 전극 SrVO₃(SVO)를 사용하였다. STO 증착 과정에서 오존(O₃)에 의해 전극/유전체 계면이 산화되어 형성된 비정질의 산화층으로 인해, 전극 비저항 증가 및 STO의 비정질 성장이 발생 함을 확인하였다. 이를 해결하기 위해 이종 리간드를 가지는 Ti 전구체의 반 응 특성을 활용한 TiO₂ self-passivation 공정을 제시하였다. Ti-OMe 리간드와 H₂O가 반응하여 TiO2 층을 만드는 메커니즘을 통해 passivation 층을 형성 하여, 계면 산화를 효과적으로 억제할 수 있었으며, STO의 결정성을 확보하 였다. 이 모델은 페로브스카이트 전극인 SVO뿐 아니라 nitride 전극인 TiN에 도 적용 가능함을 확인하였다. 또한 저온 ALD TiN 공정에서 발생하는 Cl 불순물 문제를 해결하기 위해 HBr 중간 가스를 도입한 TiCl₄ + HBr + NH₃ 우회 공정을 개발하였다. 그 결 과 성장 특성은 유지하면서 Cl 불순물을 0.3% 수준까지 저감하고, TiN 박막 의 비저항을 약 20% 감소시켰다. Dead layer 효과를 근본적으로 완화하기 위해 non-noble 금속 기반 페로 브스카이트 전극인 SrVO₃의 ALD 공정을 최초로 개발하였다. 선행된 VO₂ ALD 공정을 기반으로 SVO 박막을 구현하였으며, 전극/유전체 계면에서의 부분 결정화를 확인하였다. MIM 커패시터 전기적 특성 평가 결과, 페로브스 카이트 전극 적용 시 STO 유전막의 유전상수 향상 가능성을 확인하였다. 본 연구는 ALD 공정과 소재 설계를 통해 DRAM 커패시터에서 핵심적인 계면 산화 및 dead layer 문제를 완화하였으며, non-noble 페로브스카이트 전극의 적용 가능성을 제시함으로써 차세대 고집적 DRAM 커패시터의 유전 체와 전극막 개발에 기여할 수 있다.
more목차
Chapter 1 1
Introduction 1
1.1 Memory Hierarchy 1
1.2 Dynamic Random Access Memory (DRAM) 3
1.3 High Bandwidth Memory (HBM) 8
1.4 Atomic Layer Deposition (ALD) 11
Chapter 2 13
Theorical Background 13
2.1 DRAM capacitor dielectrics 13
2.1.1 High-k materials using ALD 18
2.1.2 Perovskite materials 19
2.2 DRAM capacitor electrodes 23
2.2.1 Nitride electrodes 23
2.3 Dead layer effect 26
2.3.1 Dead layer effect mechanism 28
2.3.2 Efforts to overcome the dead layer effect 29
2.3.3 Perovskite electrodes 31
2.4 Analysis Method 32
2.4.1 Ellipsometry 32
2.4.2 X-Ray Fluorescence (XRF) 34
2.4.3 X-Ray Diffraction (XRD) 36
2.4.4 X-Ray Photoelectron Spectroscopy (XPS) 38
2.4.5 4-probe station 40
2.4.6 Transmission Electron Microscope (TEM) 41
Chapter 3 44
Alternative reaction pathway of nitride ALD – Current DRAM capacitor electrode : TiN ALD 44
3.1 Introduction 44
3.2 Experimental Methods 50
3.3 Results and Discussions 51
3.4 Summary and conclusion 69
Chapter 4 71
Perovskite ALD – Next generation DRAM capacitor high-k/electrode : SrTiO3andSrVO3 71
4.1 Enhanced high dielectric constant of SrTiO3 film via in-situ crystallization 71
4.1.1 Introduction 71
4.1.2 Experimental Methods 75
4.1.3 Results and Discussions 76
4.1.4 Conclusion 86
4.2 Develop perovskite structure electrode, SrVO3 ALD process for the first time 87
4.2.1 Introduction 87
4.2.2 Experimental Methods 92
4.2.3 Results and Discussions 93
4.2.4 Conclusion 118
4.3 Summary and conclusion 119
Chapter 5 121
High-k/electrode heterostructure – Fabrications of MIM capacitor 121
5.1 Propose the TiO2 self-passivation model for interface oxidation of electrode 121
5.1.1 Introduction 121
5.1.2 Experimental Methods 125
5.1.3 Results and Discussions 126
5.1.4 Conclusion 136
5.2 MIM capacitor with perovskite dielectric (STO) and bottom electrode (SVO) 138
5.2.1 Results and Discussions 138
5.2.2 conclusion 142
5.3 Summary and conclusion 143
Chapter 6 145
Summary and future work 145
Chapter 7 148
7.1 References 148
7.1.1 Chapter 1 148
7.1.2 Chapter 2 149
7.1.3 Chapter 3 152
7.1.4 Chapter 4 153
7.1.5 Chapter 5 156
7.2 List of publications 156
7.3 Abstract in Korean 157
