Efficient Data and Page Table Management for Multi-Tiered Memory Systems
- 주제(키워드) Operating Systems , Computer Architecture , Memory Tiering , Address translation
- 주제(DDC) 006.31
- 발행기관 아주대학교 일반대학원
- 지도교수 김상훈
- 발행년도 2025
- 학위수여년월 2025. 2
- 학위명 박사
- 학과 및 전공 일반대학원 인공지능학과
- 실제URI http://www.dcollection.net/handler/ajou/000000034590
- 본문언어 영어
- 저작권 아주대학교 논문은 저작권에 의해 보호받습니다.
초록/요약
As memory tiering is becoming an attractive way to build cost-effective large memory systems, memory management techniques in operating systems are in- creasingly important factors in determining performance and efficiency. However, the current operating systems were primarily designed by assuming that all the memory devices have the same capabilities (e.g., DRAM). This oversimplification leads to non-optimal memory usage in tiered memory systems. This study con- ducts a comprehensive analysis of memory management schemes for both data and page tables, designed in the current Linux kernel running on a multi-tiered memory environment. As the memory tiering is built on top of NUMA architec- ture, we find that the critical factor in performance is not only the access locality but also the access tier of memory. This paper explores the design space of page management schemes for both data and page table entries to use multi-tiered memory systems effectively. Our evaluation results show that our proposed tech- niques can significantly improve performance for various workloads, compared to the stock Linux kernel, by unlocking the potential of the multi-tiered memory hierarchy.
more목차
1 Introduction 1
2 Data page management for multi-tiered memory systems 5
2.1 Background and Motivation 6
2.1.1 Large Memory Systems 6
2.1.2 Performance Characteristics 7
2.1.3 OS Support of Multi-Tiered Memory 8
2.2 Analysis of Page Management to Multi-Tiered Memory Systems 9
2.2.1 Initial Page Placement 9
2.2.2 Dynamic Placement 10
2.2.3 Page Reclamation 12
2.3 Automatic Multi-Tiered Memory 14
2.3.1 Exploiting Multi-Tiered Memory 15
2.3.2 Opportunistic Promotion and Migration 17
2.3.3 Hiding Latency of Page Demotion 20
2.4 Evaluation 22
2.4.1 Experimental Setup 22
2.4.2 Experimental Results 22
2.5 Related Work 32
2.6 Conclusion 34
3 Page table management for tiered memory systems 35
3.1 Background and Motivation 38
3.2 PTE-alloc: Keeping PTEs on Fast DRAM 41
3.2.1 Design and Implementation 41
3.3 Evaluation 43
3.3.1 Performance Comparison 44
3.3.2 Large Pages 46
3.3.3 Dynamic resizing PTE-pool 48
3.4 Discussion and Comparison with Prior Work 49
3.5 Conclusions 51
4 Integrated Data and Page Table Management 52
4.1 Evaluation 52
4.1.1 Experimental Setup 52
4.1.2 Experimental Results 52
4.1.3 Distribution of memory usage 57
4.1.4 Performance comparison with prior studies 58
4.1.5 Performance with large page 61
4.2 Related Work 63
5 Conclusion 64
5.1 Conclusion 64
Bibliography 65
