A Power Gating-based Energy-Efficient SCL Decoding Method for Polar Codes
파워게이팅 기반의 전력 효율적인 극 부호 SCL 복호 방법
- 주제(키워드) SCL , Successive Cancellation List , Decoding , 5G , Power Gating , Polar Codes
- 주제(DDC) 621.381
- 발행기관 아주대학교
- 지도교수 선우명훈
- 발행년도 2023
- 학위수여년월 2023. 8
- 학위명 석사
- 학과 및 전공 일반대학원 전자공학과
- 실제URI http://www.dcollection.net/handler/ajou/000000033118
- 본문언어 영어
- 저작권 아주대학교 논문은 저작권에 의해 보호받습니다.
초록/요약
The successive cancellation list (SCL) decoding algorithm has been proposed to enhance error correction in successive cancellation (SC) decoders for polar codes. However, implementing SCL decoding in hardware requires multiple SC cores, which leads to increased hardware complexity, power consumption, and computational complexity. In this thesis, we propose a power-efficient SCL decoding architecture that utilize power gating techniques to address these issues. The proposed power gating-based SCL decoder architecture operates in the following two scenarios. The first scenario involves shutting off a subset of the decoding cores for the entire decoding process, using power gating. This approach significantly reduces computational complexity by up to 75% in low noise environments. The second scenario achieves low power consumption by selectively shutting off some decoding cores during specific parts of the decoding process. This method results in up to 19% of reduction in computational complexity. The proposed architecture and scenarios are also evaluated in terms of error correction performance, measured by the frame error rate (FER). The two scenarios in which the proposed architecture operates provide us with a wider range of performance options that span from a conventional SCL with a list size of L−M to a conventional SCL with a list size of L.
more목차
I. Introduction 8
II. Review of Polar Code 10
A. Polar Codes and Successive Cancelation Decoding 10
B. Successive Cancellation SC and List (SCL) Decoding 11
C. Hardware Architecture of SCL Decoders 13
III. Proposed Power Efficient SCL Decoding Method 16
A. Power gated SCL 16
B. Power Gating Scenario I 18
C. Power Gating Scenario II 19
IV. Results 21
A. Error Correction Performance 21
B. Computational Complexity 22
V. Conclusions 24
References 25
