Towards a Robust, Scalable and High-Performance Next Generation NVM Based Storage Architecture
- 주제(키워드) Thesis
- 발행기관 아주대학교
- 지도교수 Tae-Sun Chung
- 발행년도 2020
- 학위수여년월 2020. 2
- 학위명 박사
- 학과 및 전공 일반대학원 컴퓨터공학과
- 실제URI http://www.dcollection.net/handler/ajou/000000029908
- 본문언어 영어
- 저작권 아주대학교 논문은 저작권에 의해 보호받습니다.
초록/요약
Although flash memory solid state drives (FSSDs) outperform traditional hard disk drives (HDDs), their performance still fails to cope up with the perennial doubling speeds of microprocessors (CPUs) and network bandwidth, regardless of the available high bandwidth in computer systems. This is mainly because flash memory has to slowly write out-of-place which further induces erase and garbage collection (GC) operations apart from the high risk of further delay caused by access conflict. Moreover, FSSDs employing a cache mapping table (CMT) in DRAM suffer from a heavy cache-miss penalty when exposed to high miss-rate workloads environments which further degrade FSSD performance. Such implementations also fail to recover without page faults and amplified read operations whenever the system experiences an unexpected power-cut because of the sync interruption between volatile DRAM and flash mappings. To alleviate this performance gap, various semiconductor institutions like Intel, Micron, Samsung, and Hynix have developed faster and scalable non-volatile memory (NVM) technology for use as main memory but so far none have produce a full NVM Phase Change Memory solid state drive (PCM-SSD). If we can use PCM as secondary memory in SSD, we can build a future PCM-SSD (PSSD) to replace the slow traditional FSSD. However, a careful design, on how to present the PSSD as a block device to the host while concealing the underlying PCM energy consumption and endurance weaknesses is essential. Moreover, the management of PCM in-place-updates ability and bit-addressability should be not be overlooked. In this dissertation, we propose a hardware assumption of an NVM-PCM to replace NAND-flash memory as a next generation storage memory in storage systems devices like SSDs. We introduce a PCM file translation layer called PhaseFTL. Our FTL can manage the address mappings from the host file system to PCM and can hide the PCM energy consumption and limited lifespan constrains together with providing an efficient wearleveling algorithm for PCM blocks to wear down evenly. Moreover, PhaseFTL also efficiently exploit the bit-addressability and in-place-update ability of PCM apart from being robust from faults caused by sudden or unexpected power failures, for example. When such occurs, our proposed system has effective fault recovery mechanisms that further determines how the CMT is constructed or reconstructed during the system recovery process. Experimental results show that our PSSD can improve the overall SSD performance by 69% on average compared to traditional FSSDs while our PhaseFTL can efficiently manage the PSSD operations whilst hiding its endurance weakness by propagating more write traffic to DRAM and less to PCM cells. Furthermore, our system outperforms traditional approaches on both lifespan management and robustness apart from the reduction of access conflicts.
more목차
1 Introduction 1
1.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.2 Contributions of This Dissertation . . . . . . . . . . . . . . . . . . . . . . . . 9
1.2.1 A PCM-SSD (PSSD) Architecture . . . . . . . . . . . . . . . . . . . . . 9
1.2.2 FTL Design for PSSDs . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.2.3 PSSD Fault Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.2.4 PCM Lifespan Management . . . . . . . . . . . . . . . . . . . . . . . . 11
1.3 Thesis Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2 Background 13
2.1 PCM Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.2 PCM Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.2.1 Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.2.2 Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.2.3 PCM Endurance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.3 Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.3.1 PCM implementation as an SSD . . . . . . . . . . . . . . . . . . . . . 19
2.3.2 PCM FTLs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3 A Scalable and Robust High Performance Next Generation PCM-SSD 26
3.1 Design and Implementation of our PSSD . . . . . . . . . . . . . . . . . . . . 26
3.2 Proposed Future PSSD Architecture . . . . . . . . . . . . . . . . . . . . . . . 28
3.2.1 PSSD1 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.2.2 PSSD2 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.3 PhaseFTL for PCM-SSDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.3.1 PhaseFTL Mapping Operations . . . . . . . . . . . . . . . . . . . . . . 33
PCM Page-Mapping Operation . . . . . . . . . . . . . . . . . . . . . . 36
PCM Block-Mapping Operation . . . . . . . . . . . . . . . . . . . . . 37
3.3.2 PSSD Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.3.3 PSSD Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.4 PCM Lifespan Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.5 PCM fault Tolerance Management . . . . . . . . . . . . . . . . . . . . . . . . 42
Fast Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Hot and Cold Page Separation . . . . . . . . . . . . . . . . . . . . . . 49
4 Performance Evaluation 51
4.1 Experimental Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
4.1.1 Workloads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
4.1.2 Configuration Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
4.1.3 Simulation Environment . . . . . . . . . . . . . . . . . . . . . . . . . . 59
4.2 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
4.2.1 Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
4.2.2 Lifespan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
4.2.3 CMT Construction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
4.2.4 Fault Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
5 Conclusions 72
A List of Publications 83
A.1 SCI/SCIE Journal Papers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
A.2 International Conference Papers . . . . . . . . . . . . . . . . . . . . . . . . . 84
