과도 응답 성능을 개선한 저전력 전압 레귤레이터 설계
Design of the Low Power Low-Dropout Regulator with Transient Response Improvement
- 주제(키워드) Low dropout(LDO) regulator , undershoot reduction , settling time reduction , low quiescent current
- 발행기관 아주대학교
- 지도교수 권익진
- 발행년도 2019
- 학위수여년월 2019. 2
- 학위명 석사
- 학과 및 전공 일반대학원 전자공학과
- 실제URI http://www.dcollection.net/handler/ajou/000000028872
- 본문언어 영어
- 저작권 아주대학교 논문은 저작권에 의해 보호받습니다.
초록/요약
This paper proposes an external capacitor-less low-dropout (LDO) regulator with undershoot and settling time reduction technique for fast transient response. In the proposed LDO, a feedback capacitor is applied instead of a complicated voltage-spike detection circuit to reduce undershoot voltage and settling time without consuming additional quiescent current. When the undershoot voltage occurs in the load transient response, the gate charging current of the pass transistor is rapidly increased by the current flowing in the feedback capacitor to reduce the undershoot voltage. When the overshoot voltage occurs, the gate charging current to reduce the settling time. The proposed LDO regulator is implemented with a 0.18 μm CMOS process and consumes a quiescent current of 3.0 μA at a minimum load current of 0.1 mA and 230 μA at a maximum load current of 50 mA. Compared with the conventional LDO regulator, the proposed LDO regulator reduces the undershoot voltage by 53.3 % and the settling time by 55.5 % without consuming additional quiescent current.
more목차
Chapter 1. Introduction 1
Chapter 2. Conventional LDO regulator 2
Chapter 3. Proposed LDO regulator 5
Chapter 4. Simulation Results 14
Chapter 5. Measurement Results 20
Chapter 6. Conclusion 34
Publications 35
References 36
국문 요약 38
