비트-직렬 생성기를 활용한 저면적, 높은 처리율을 가지는 LDPC 복호기 구조
Low-complexity and High-throughput LDPC Decoder Architecture Using Bit-serial Generators
- 주제(키워드) Area-time complexity , bit-serial scheme , low-complexity design , low-density parity-check (LDPC) decoder , minimum-value generator , min-sum algorithm.
- 발행기관 아주대학교
- 지도교수 선우명훈
- 발행년도 2017
- 학위수여년월 2017. 2
- 학위명 박사
- 학과 및 전공 일반대학원 전자공학과
- 실제URI http://www.dcollection.net/handler/ajou/000000024233
- 본문언어 영어
- 저작권 아주대학교 논문은 저작권에 의해 보호받습니다.
초록/요약
Low-density parity-check (LDPC) codes are one of the block coding techniques that can approach the Shannon’s limit within a fraction of a decibel for high block lengths. Recently, LDPC codes have been chosen to be part of many digital communication systems such as IEEE 802.11ad, IEEE 802.15.3c, and 5G telecommunications standard. As the standards are used to provide multi-Gbps throughput in mobile and portable computing devices, the codes allow effective hardware implementation and simultaneously achieve multi-Gbps decoding. The first two minimum values generator is the most complex module of LDPC decoder. This thesis introduces two low-complexity generators. The proposed bit-serial generator reduces the hardware complexity by approximately 26% compared with the existing bit-serial generator. Since the proposed generator requires long latency, a LDPC decoder using the bit-serial scheme is not suitable for multi-Gbps throughput. To achieve short latency, a bitwise generator is proposed, which is constructed using serially connected w bit-serial generators, where w is the word length. The bitwise generator takes only one clock cycle, reducing the hardware complexity by 15%. As the case studies, I have designed two LDPC decoders, flooding and layered schemes, based on a bitwise generator for the 802.11ad standard with the 90-nm CMOS technology. Compared to conventional decoders for 802.11ad, the decoders achieve the most efficient throughput-area ratio.
more목차
Abstract vi
List of Figures vii
List of Tables x
I. Introduction 1
II. Overview of LDPC Codes 6
A. Linear Block Code 6
B. LDPC Code 7
C. QC-LDPC code 9
D. LDPC Decoding Algorithms 12
1. Sum-Product (SP) Decoding Algorithm 12
2. Min-Sum (MS) Decoding Algorithm 15
3. Normalized and Offset MS Decoding Algorithms 16
4. Performance comparisons 17
E. Classification of LDPC Decoder Architectures 21
1. Serial Architecture 22
2. Fully-parallel Architecture 24
3. Partially-parallel Architecture 27
III. LDPC Decoders 33
A. Non-Overlapping Layers and Dynamic Column Shifting 33
1. QC-LDPC codes for 802.11ad 39
B. Design A 43
1. VN unit 45
2. CN unit 47
3. Switching Network 50
4. Pipeline 51
C. Design B 54
IV. Architectures for Finding the First Two Minimum Values 56
A. Bit-parallel Generators 57
B. Bit-serial Generators 61
C. Bit-serial Generator Reusing Flags (BSG) 68
1. Algorithm for BSG 68
2. Architecture for BSG 73
D. Bitwise Generator Reusing Flags (BWG) 80
E. Implementation Results 82
V. Experimental Results 87
A. Quantization 87
B. Implementation Results 90
VI. Conclusions and Future Work 94
A. Conclusions 94
B. Future Work 95
Bibliography 97
