Log-Buffer Aware Cache Replacement Policy for Flash Storage Devices
- 주제(키워드) flash memory , cache management , page replacement policy , flash translation layer , embedded devices
- 발행기관 아주대학교
- 지도교수 Tae-Sun Chung
- 발행년도 2016
- 학위수여년월 2016. 8
- 학위명 석사
- 학과 및 전공 일반대학원 컴퓨터공학과
- 실제URI http://www.dcollection.net/handler/ajou/000000022949
- 본문언어 영어
- 저작권 아주대학교 논문은 저작권에 의해 보호받습니다.
초록/요약
In recent times, flash memory has been widely used in embedded devices and enterprise computing environments because of its many advantages, which includes shock resistance, low energy consumption, non-volatile nature and high I/O speed. However, flash memory hardware also possesses characteristics such as erase-before write, a limited number of erase cycles and asymmetric I/O costs among read, write, and erase operations, where the cost of write and erase operations are much higher than that of read operations. Hence, there is the need for the cache-replacement policy in flash-based systems to consider the asymmetric I/O costs. Previous studies on cache management including least recently used (LRU), clean-first LRU (CFLRU) and cold clean-first LRU (CCF-LRU) focused mainly on to reducing the write access to flash memory by evicting clean pages before dirty pages, and they do not consider how the evicted page would be treated by the flash memory. This resulted in performance degradation. Flash aware buffer-management (FAB) tries to evict pages considering the inner structure of flash memory but there are problems related to the high cache-miss ratio and the generation of a large number of write operations to the flash memory. In this paper, we propose a log-buffer aware (LBA) cache-replacement policy that not only tries to reduce the number of write accesses to flash memory as well as the high cache hit ratio, but also evicts pages while considering the log-block associativity problem of log-based flash translation layers (FTLs). Experimental results show that compare to previous studies, the proposed cache-replacement policy is more effective for higher cache-hit ratio and for reducing the garbage-collection overhead of flash memory by increasing the partial merge and switch operations.
more목차
CHAPTER 1. Introduction 1
CHAPTER 2. Background and Related Work 5
2.1 Background 5
2.1.1 System Architecture of Flash Memory 5
2.1.2 Log Buffer-Based FTLs 12
2.1.3 Flash-Aware Buffer Schemes 14
CHAPTER 3. Log-buffer Aware Cache-replacement Scheme 19
3.1 Overview 19
3.2 Page Eviction Rules 21
3.3 Description 22
CHAPTER 4. Simulation 26
4.1 Experimental setup 26
4.2 Results Evaluation 28
4.2.1 Number of write operations 28
4.2.2 Average associativity 31
4.2.3 Number of switch operations 32
4.2.4 Number of cache hits 33
CONCLUSION 34
REFERENCES 35
