An Efficient and Reliable Flash Translation Layer for Chip-Level-Parallel Flash Memory
- 주제(키워드) Flash Memory , Flash Translation Layer
- 발행기관 아주대학교
- 지도교수 정태선
- 발행년도 2012
- 학위수여년월 2012. 8
- 학위명 박사
- 학과 및 전공 일반대학원 컴퓨터공학과
- 실제URI http://www.dcollection.net/handler/ajou/000000012818
- 본문언어 영어
- 저작권 아주대학교 논문은 저작권에 의해 보호받습니다.
초록/요약
Flash memory offers attractive features, such as non-volatile, shock resistance, fast access, and low power consumption. As flash memory receives much attention in data storage market, low priced multi-level-cell (MLC) flash memory has been widely adopted in the large-scale storage systems despite of its low performance. In order to hinder the low performance of MLC-flash memory, there has been a system design which optimizes chip-level-parallelism. This design enlarges the unit of page and block thus simultaneously executing operations on multiple chips. Unfortunately previous algorithms of flash translation layer (FTL) generate many unused sectors within each page thus creating unnecessary write operations. As the concept of the chip-level-parallelism has been proposed recently, previous FTL algorithms show low compatibility to the chip-level-parallel flash memory. They execute unnecessary erase operations due to the low space utilization. As a solution, we propose “Hybrid Associative FTL (Hybrid-FTL)” for enhancing the performance of the chip-level-parallel flash memory system. The hybrid-FTL reduces the number of write operations by fully utilizing all the unused sectors. Furthermore, it reduces overall number of erase operations by using the state transition and reallocation blocks. It also prolongs the durability of the chip-level-parallel flash memory by modifying the merge operation. We have compared hybrid-FTL to previous FTL algorithms by simulating them on 1 Tbytes of 4-chip-parallel flash memory. We have retrieved various traces from PCs using different file systems (NTFS and EXT3) and embedded devices. According to our experiment results, the hybrid-FTL significantly reduces the number of write operations by avoiding the sub-page-sets. Furthermore, it reduces the number of erase operations and evenly distributes them by “Hybrid Associative Sector Translation (HAST)”.
more목차
Contents
Acknowledgements i
Abstract ii
List of Figures v
List of Tables vi
Chapter 1 Introduction 1
1.1 Chip-level-parallel Flash Memory 3
1.2 Page-set Buffering Algorithm 4
1.3 Performance Enhancing Algorithms 4
1.4 Durability Enhancing Algorithms 5
1.5 Thesis Outline 5
Chapter 2 Background of Flash Memory 7
2.1 Basic Features 7
2.2 Features in Large Block Flash Memory 9
2.2.1 Single-/Multi-level-cell Flash Memories 9
2.2.2 Sequential Write Restriction and NOP Restriction 10
2.2.3 Random Data Out/In 11
2.3 Flash Translation Layer 12
2.3.1 Basic Mapping Algorithms 14
2.3.2 Static and Dynamic Allocation 18
Chapter 3 Literature Review 21
3.1 Chip-level-parallel Flash Memory System 21
3.2 Page-set Buffering Algorithms 24
3.3 Performance Enhancing Algorithms 26
3.4 Durability Enhancing Algorithms 28
3.5 Power-off Recovery 32
3.5.1 Block-level Management 32
3.5.2 Sector-level Management 33
3.5.3 Erase Count Block 34
Chapter 4 Hybrid Associative Flash Translation Layer 36
4.1 Hybrid Page-set Buffering Algorithm 37
4.1.1 Key Idea 37
4.1.2 Hybrid Page-set Buffering Algorithm 39
4.2 Hybrid Associative Sector Translation 43
4.2.1 Key Idea 43
4.2.2 Hybrid Associative Sector Translation 46
4.3 Wear-Leveling for Hybrid Associative Sector Translation 49
4.3.1 Key Idea 49
4.3.2 Merge Operation in Hybrid Associative Sector Translation 52
4.4 Power-off Recovery 57
Chapter 5 Performance Evaluation 59
5.1 DRAM and Flash Memory Requirement 59
5.2 Evaluation for Mapping Algorithms 62
5.3 Environment Setup 63
5.4 Effect of Hybrid Page-set Buffering Algorithm 65
5.5 Effect of Hybrid Associative Translation Scheme 69
5.6 Effect of HAST Merge Operation 72
Chapter 6 Conclusion 77
References 80
