저속 근거리 무선 개인 통신망 적용을 위한 극소전력의 CMOS 송수신기
AN ULTRA LOW-POWER CMOS TRANSCEIVER FOR LOW-RATE WIRELESS PERSONAL AREA NETWORK APPLICATIONS
- 주제(키워드) SoC , transceiver , low-power
- 발행기관 아주대학교
- 지도교수 이해영
- 발행년도 2011
- 학위수여년월 2011. 8
- 학위명 박사
- 학과 및 전공 일반대학원 전자공학과
- 실제URI http://www.dcollection.net/handler/ajou/000000011879
- 본문언어 영어
- 저작권 아주대학교 논문은 저작권에 의해 보호받습니다.
초록/요약
A fully integrated 2.4 GHz CMOS RF transceiver and MCU (System-on-Chip) with short range wake-up function for low-rate wireless personal area network (LR_WPAN) applications in a 0.18-μm CMOS technology is implemented and measured. The chip fully complies with the IEEE 802.15.4 standard. The target applications are small device, like remote-controller, ESL (Electronic Shelf Label), and grasses for 3D TV with particularly tight constraints on power consumption and size. The single chip transceiver incorporates an I/Q modulator and demodulator, an integrated RF synthesizer with a stacked voltage controlled oscillator (VCO), a receiver including the antenna diversity, and passive wake-up circuits using rectifiers. The receiver has a low-IF architecture with an intermediate frequency of 2 MHz. This architecture allows implementations of the channel filter on wafer. Therefore, an external bulky and expensive filter for the traditional Superheterodyne architecture can be eliminated. The implemented active filter is active RC type and includes an analog integrator and a digital tuning engine to support the realization of an automatic frequency tuning scheme. In order to reduce the power consumption while operating the receiver mode, the high-Q inductor on wafer and the current reuse topologies are adopted in the LNA and the down-conversion mixer, respectively. An antenna diversity scheme with internal switch is applied for avoiding the dead zone during communication. A fractional frequency synthesizer is designed for local frequency. The VCO's oscillation frequency sets to 5 GHz, twice of RF carrier frequency to make I/Q signal, prevent pulling effect of VCO and reduce a phase noise of VCO. The VCO is one of the most critical blocks consuming the power in the transceiver. For the low-power consumption and high-frequency operation, the VCO and the divider-by-2 are stacked. A Direct-Conversion architecture is used in the transmitter. This architecture is attractive for the following reasons: direct up-conversion produces less mixing product spurs, it requires fewer filters, and the lower number of parts helps minimize the current consumption. In order to obtain the ultra low power consumption in sleep-mode, RC-OSC operating under 200 nA, Regulator operating under 200 nA for sleep mode, quick start block for crystal oscillator, and the passive wake-up circuit are implemented in this transceiver. The power consumption in the sleep and active mode is improved by using a passive wake-up circuits and a stacked VCO, respectively. The transmitter achieves less than 5.0 % error vector magnitude (EVM) at 5 dBm output and the receiver sensitivity is -101 dBm. The sensitivity of the wake-up block is -29.8 dBm. The current consumption is under 14.3 mA for data receiving mode, 16.7 mA for transmitter and less than 600 nA for sleep mode from a 1.8 V power supply. Consequently, I analyzed, implemented, and measured the ultra low-power SoC complied with IEEE 802.15.4. In order to reduce the power consumption of the transceiver, I used a lots of methods such as the high Q inductor with negative gm, the stacked VCO, the current reuse Mixer, the ultra low power sleep regulator, the ultra low power RC OSC, and no current consumed passive wake-up circuit. The proposed transceiver holds ultra-low power dissipation in the receiving, transmitting, and sleep modes with the reasonable performance because several techniques are used to reduce power consumption. Therefore, this system can be adopted for ultra-low power systems that require more than 5 years of the operation using a single Lithium-Ion battery such as electronic shelf labels (ESL), remote controllers, and glasses for 3D TV.
more목차
Acknowledgement i
Abstract iii
I. Introduction 1
A. Motivation 1
B. Research goal 3
C. Dissertation organization 5
II. The IEEE 802.15.4 LR-WPAN System 7
A. System overview 7
B. PHY Specifications for the IEEE 802.15.4 10
III. Low Power Transceiver Architecture Selection 20
A. Receiver architecture 20
1. Superheterodyne receivers 20
2. Direct-conversion receiver 22
2-1. DC offset 26
2-2. Flicker noise 27
3. Low-IF receiver 28
4. Digitalized receiver 31
B. Transmitter Architecture 32
1. Direct-conversion transmitter 32
2. Two-step transmitter 34
3. Polar transmitter 35
C. Transceiver architecture selection for low-power 37
IV. System Planning for Low Power 41
A. Transceiver requirements 41
1. Receiver specifications 41
2. Transmitter specifications 46
B. System simulation for low power 48
1. Low power consumption and RF budget 48
2. System simulation 55
V. Low Power Techniques for RF Transceiver 63
A. CMOS technology approaches 63
1. Active components 63
2. Passive components 67
B. Circuits approaches 67
1. Common metrics 67
2. Amplifier (LNA) 71
3. Mixer 74
4. Voltage control oscillator 75
C. System Approaches 77
1. Transceiver architectures 77
2. Wake-up scheme 80
D. Operation approaches 81
E. Comparison of other works 83
VI. Parameters of The TR for CMOS Process 85
A. 1.8 V Analog transistors 85
B. 3.0 V Analog transistors 88
VII. Low Power Design of the Receiver 92
A. Low-power & low-noise amplifier 92
1. Input matching for minimizing the NF 94
2. LNA topologies for low power 101
3. Negative gm for low power consumption 105
4. RF switch for antenna diversity 108
5. Implementation of the low power LNA 108
6. Simulation and measurement results 114
B. Low-power down conversion mixer 115
1. General consideration 118
2. Implementation of the low power mixer 123
3. Simulation and measurement results 123
C. Band-pass filter and programmable gain amplifier 125
1. BPF, and PGA architecture 125
2. Simulation and measurement results 130
D. Analog to digital converter 136
E. Antenna selection block 141
1. Antenna selection block architecture 141
2. Simulation and measurement results 145
F. RX TOP simulation and measurement results 150
VIII. Low Power Design of the Transmitter 157
A. Digital-to-analog converter 157
B. TX low pass filter 163
C. TX up-conversion mixer 166
D. TX drive amplifier 166
E. TX TOP simulation and measurement results 169
IX. Low Power Design of the PLL 175
A. VCO with DIV2 for low power 175
B. LO buffer 178
C. Divider 184
D. Charge pump and loop filter 189
E. Phase frequency detector 192
F. PLL TOP simulation and measurement results 194
X. Other Blocks for Low Power 198
A. Regulator for sleep mode 198
B. RC oscillator for sleep mode 201
1. RCOSC architecture 201
2. Auto calibration 205
C. Quick start oscillator for low power 209
1. Quick start OSC architecture 209
2. Measurement results 216
D. Passive wake-up circuit for low power 219
1. Passive wake-up architecture 219
2. Simulation and measurement results 221
XI. Transceiver Operating Process for Low Power 226
XII. Summary 229
XIII. Appendix A 234
XIV. Bibliography 254
Vita 269
List of Publications (Paper) 270
List of Publications (Patent) 272
Abstract in Korean 274
Acknowledgements in Korean 277
